5D Perception on-the-edge®
Today’s radar sensor outputs a point cloud and waits for an external GPU to make sense of it. 5D Perception on-the-edge moves the AI perception onto the radar’s own SoC — running the URMAP Lite model alongside the DSP chain on a single chip. No external GPU, no extra box, no extra wiring. The sensor outputs detected, classified and tracked objects directly.
10+ FPS
perception on TDA4
7 cores
shared with DSP chain
0
external GPUs needed
50
edge sensors in deployment
Applications
Where the radar sensor itself has to do the thinking.
Automotive
Mass-market ADAS where adding a dedicated GPU per radar sensor is cost-prohibitive. 5D Perception on-the-edge gives OEMs perception-equipped radar sensors at price points that work for volume vehicles, not just premium platforms.
Tier-1 sensors
Radar module suppliers can ship an intelligent sensor — perception output, not just a point cloud. The Denso Gen8 A-Sample is a live deployment of this model targeting 50 edge sensors built around the TI TDA4.
Industrial
Mining, agriculture, warehouse robotics — environments where power, cooling and physical space at the sensor are severely constrained. AI perception ships in the radar; no extra hardware required.
Cost-sensitive
Robotics platforms, autonomous shuttles, anywhere every watt and every dollar of BOM matters. 5D Perception on-the-edge runs on standard commercial SoCs — no specialist GPU silicon needed.
How it works
Distilling flagship radar AI into a model that fits on the chip.
STEP 01
Distill from flagship URMAP
URMAP Lite isn’t a separately-trained model. The intelligence of Provizio’s flagship URMAP — trained on diverse data from 30+ OEMs — is knowledge-distilled into a compact CNN/Transformer hybrid. Same training base, edge-sized footprint.
Diagram · knowledge distillation
STEP 02
Edge-tuned architecture
Weights are highly compressed; tensors are optimised for minimal RAM. The architecture is engineered around the constraints of automotive SoC silicon — fitting in cache, maximising the work done by every clock cycle the hardware gives the perception task.
Diagram · compressed model footprint
STEP 03
Coexist with the DSP chain
On a TI TDA4, seven C7x/MMA DSP/accelerator cores are split between two workloads: a subset run the URMAP Lite inference; the rest run the radar signal-processing chain. Heterogeneous core allocation is what makes parallel perception + DSP on one chip feasible.
Diagram · 7-core allocation map
STEP 04
ONNX → TIDL compile pipeline
Models built in standard ONNX are compiled automatically into TIDL (Texas Instruments Deep Learning) artifacts. That lets URMAP Lite run on TI’s hardware-accelerated DL engine, not a generic software inference path — covering both TDA4AEN and TDA4VM platforms.
Diagram · ONNX → TIDL pipeline
STEP 05
Microservice + DDS interface
The perception stack runs as a self-contained microservice on the SoC. Radar point cloud in over DDS, detected/classified/tracked objects out — identical interface to the full URMAP model. Downstream code doesn’t know whether perception is running on Orin or on the radar’s own chip.
Diagram · DDS microservice interface
Featured deployment
Denso A-Sample: 50 edge sensors targeted on TI TDA4.
The Denso Gen8 A-Sample project is the live deployment of 5D Perception on-the-edge — an 8×8 TI radar front-end paired with a TDA4 SoC, running URMAP Lite alongside the DSP chain. Target: 20 FPS perception, 50 edge-sensor units. The preprocessing and post-processing C++ stack is already running as a microservice on TDA4. TI flagged strong interest at CES 2026 in scaling this pattern across their SoC catalogue.
- Live Denso Gen8 A-Sample deployment — 50 edge sensors targeted
- URMAP Lite C++ microservice running on TDA4
- Automated ONNX-to-TIDL conversion pipeline built
- TI partnership engagement following CES 2026
PLACEHOLDER · TDA4 edge-sensor reference design
Where it sits on the compute spectrum
Three tiers of radar AI compute — and where this product fits.
Provizio’s perception stack scales across compute tiers. Pick the tier that matches your BOM and your performance target.
GPU CLASS
Full URMAP®
The full URMAP model on dedicated GPU silicon — NVIDIA DRIVE Orin and similar. Maximum throughput, complete perception feature set including SLAM accumulation, freespace and occupancy gridmap. Highest BOM, highest performance.
Where it runs: NVIDIA Orin · external GPU
SoC CLASS
URMAP Lite (this page)
URMAP Lite distilled from the flagship model, running directly on the radar’s SoC alongside the DSP chain. Same perception intelligence in a compact, power-efficient footprint. The mass-market path to perception-equipped radar.
Where it runs: TI TDA4 · on the radar chip
HYBRID
Satellite + central compute
For multi-radar architectures, some platforms split the compute: lightweight perception on each satellite radar’s SoC, with heavier fusion and SLAM on a central NVIDIA Thor or similar. Both workloads use URMAP variants on the same training base.
Where it runs: Multi-chip · split compute
Integration
Same interface, smaller chip
5D Perception on-the-edge produces the same DDS perception output as the full URMAP model. That means you can prototype on GPU hardware and deploy to the SoC without changing your downstream code. The platform-agnostic model design means it isn’t locked to one SoC family — TI TDA4 is the current focus, but the ONNX-first pipeline ports to other embedded deep-learning targets.
- TI TDA4AEN and TDA4VM platforms
- ONNX → TIDL automated compilation
- Heterogeneous core allocation (7 × C7x/MMA)
- DDS perception output (same as full URMAP)
- Microservice C++ runtime
- Platform-agnostic ONNX starting point
Questions, answered
5D Perception on-the-edge FAQ
It’s the edge-deployed version of Provizio’s 5D Perception stack. The core is URMAP Lite — a knowledge-distilled version of the flagship URMAP perception model — running directly on the radar’s SoC (currently the TI TDA4) alongside the DSP chain. No external GPU or compute unit required. The sensor outputs detected, classified and tracked objects via DDS, the same interface as the full URMAP model.
Same training base, same output interface — different compute footprint. URMAP Lite uses a compact CNN/Transformer hybrid architecture with highly compressed weights, designed to fit within the memory and power budget of standard automotive SoCs. The intelligence is distilled from the full URMAP model; URMAP Lite is not separately trained from scratch.
Through heterogeneous core allocation. A TI TDA4 has seven C7x/MMA DSP/accelerator cores. Provizio dedicates a subset to deep-learning inference (URMAP Lite) and the rest to the radar signal-processing chain. The allocation balance is the engineering work that makes stable 10+ FPS perception possible without starving the low-level DSP of resources.
Currently the deepest integration is with TI TDA4 (covering TDA4AEN and TDA4VM, with an automated ONNX-to-TIDL compilation pipeline). The underlying model design is platform-agnostic — ONNX is the common starting point. As customer requirements dictate, the same model can be compiled to other embedded deep-learning targets.
The Denso Gen8 A-Sample project — TI 8×8 radar front-end + TDA4, targeting 50 edge sensors at 20 FPS perception — is the lead live deployment. The C++ microservice is running on TDA4 today; the core-allocation tuning is ongoing to hit stable frame rates across the perception/DSP workload split.
Put the AI on the chip.
If you’re designing a radar sensor that needs to ship perception output without an external compute box, 5D Perception on-the-edge is the path. Talk to our team about your target SoC and your target framerate.